1. Field of the Invention
This invention generally relates to system-on-chip (SoC) power management and, more particularly, to a system and method for enabling processors in a multi-processor SoC by using a power management controller to monitor ingress and egress processor queue levels.
2. Description of the Related Art
Some conventional processors provide a mechanism for software (SW) to issue speed up or slow down commands to a programmable engine. Usually this mechanism is driven from a central power management SW driver associated with an operating system. Such mechanisms are based purely on the software and operating system view of workload demand. These mechanisms work well for computing applications whereby the operating system is charged with scheduling the processor resources and has complete control over what is executing when. However, for applications that are dominated by input/output (IO) processing, where the workload is dependent on a set of external events such as packet arrivals and departures, the operating system and associated device drivers do not have enough pre-knowledge of pending load status. Without such pre-knowledge, the processors must be kept in the fully “on” status in order to react to the worst case loading conditions.
Some existing systems make use of a micro-controller to manage device level power. As an example, the microcontroller may be primarily responsible for sequencing voltage, frequency, and even transistor bias in order to achieve a particular power performance mix. Commands to such a microcontroller are usually driven from a single device driver under an operating system. As described earlier, the commands are based on the software observed workload.
Dynamic voltage and frequency scaling (DVFS) permits processor frequency and voltage to be dynamically changed based on the software workload requirements. In some systems, DVFS is controlled by a dedicated side band interface between each software controlled processor and a central power management controller (PMC). Each processor typically has a dedicated set of control registers that it writes to change states. If the processor's OS wants a little bit more or less power, it writes to its corresponding control register using a device driver. In a multi core system using asymmetric multiprocessors there is no single unified device driver, but instead, a set of device drivers for each OS. These device drivers are unaware of each other.
In other prior art, a system level microcontroller may be responsible for system level power management. An example might be a notebook computer containing suspend states. The micro controller may be used to sequence the system back to normal operational state in the event of external stimulus such as an arriving wake up packet at an Ethernet port.
The problem with the above-mentioned systems is that none of them incorporate a means for making power management decisions based upon actual workload observation. None of these systems use a set of programmed thresholds that help the processing engine determines the optimal voltage and frequency calculation based on quality of service information. Further, for multiprocessing systems, the prior art is usually dependent on a single host-to-SW driver to manage power. Such schemes are not extensible to asymmetric multiprocessor systems. Even more so, they do not comprehend heterogeneous multiprocessor systems which may be comprised a mix of general purpose processors and accelerators.
Symmetric multiprocessing (SMP) is a system of computer architecture where two or more identical processors are connected to a single shared main (physical) memory. Further, each processor participating in the SMP system must coordinate together to manage memory. SMP systems permit any processor to work on any task, no matter where the data for that task is located in memory. SMP systems can move tasks between processors to balance the workload efficiently. Asymmetric multiprocessing (AMP) refers to a system whereby multiple processors independently run operating systems with no awareness of each other. In this case, there is no memory management coordination between the operating systems. Heterogeneous processors in this context are processors that have different programming models especially where memory management is concerned.
Examples of the prior art are found across the Intel and AMD x86 processor line. Microcontrollers for system power control are found in Apple and other notebooks. And last but not least, power management of multi core mobile appliances such as advanced mobile phone chip sets has existed for some time.
It would be advantageous if process power in a multi-processor system could be more efficiently managed using a means to directly measure the actual workload.
It would be advantageous if the actual workload could be measured by determining the number of messages in queue for processing.